As an enabling technology, the high-K metal gate module was introduced for modern logic devices (45 nm technology node and beyond) for performance improvement. The replacement metal gate (gate-last) approach has become the mainstream technology for the high-k metal gate module in advanced device manufacturing, especially for 20 nm and beyond. For the replacement metal gate module, several key CMP processes, including selective oxide/nitride polishing, poly open polishing (POP) and self aligned contact (SAC), must be optimized to meet the stringent planarity and defect requirements. While there exist multiple processes for fabricating the devices, frequently silicon nitride is used as a capping layer and as an etch stop layer. For POP and SAC steps, it is very challenging to selectively remove a capping silicon nitride layer and to stop well on either the polysilicon gate or oxide layer for accurate gate height control, and to minimize oxide loss or erosion around the gate. Meanwhile, erosion on the POP step may lead to metal residue, such as aluminum, following deposition of a metal layer and subsequent metal polishing to form the gate.
There are typically two steps of CMP polishing in the replacement metal gate (RMG) process: (i) removing bulk oxide, topography planarization, and selectively stopping on the nitride stress and cap layers, and (ii) a higher rate of nitride polishing with tunable selectivities to oxide. Typically, silica based or ceria based slurries for the first step should be higher selectivity of oxide to nitride. In practice, there will be non-uniformity of nitride loss and surrounding oxide dishing. It is critical for POP polishing to minimize this surface topography, or it may lead to poor gate height control and to defectivity in subsequent metallization steps. In general, a flexible nitride to oxide selectivity is needed for POP polishing to meet the stringent requirements in the RMG process. The challenge in SAC similarly requires a higher selectivity of nitride to oxide which provides excellent planarization efficiency and topography.
Thus, there remains a need in the art for polishing compositions and methods that can provide desirable tunable selectivity of silicon nitride, silicon oxide, and polysilicon and that have suitable removal rates.